发明名称 MEMORY/LOGIC CONJUGATE SYSTEM
摘要 In a memory/logic conjugate system, a plurality of cluster memory chips each including a plurality of cluster memories (20) including basic cells (10) arranged in a cluster, the basic cell including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus (11) including a through-via, an arbitrary one of the basic cells is directly accessed through the multibus from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell is switched to a logic circuit as conjugate.
申请公布号 US2013061004(A1) 申请公布日期 2013.03.07
申请号 US201213644635 申请日期 2012.10.04
申请人 OTSUKA KANJI;ITO TSUNEO;SATO YOICHI;YOSHIDA MASAHIRO;YAMAMOTO SHIGERU;KOYAMA TAKESHI;TANBA YUKO;AKIYAMA YUTAKA 发明人 OTSUKA KANJI;ITO TSUNEO;SATO YOICHI;YOSHIDA MASAHIRO;YAMAMOTO SHIGERU;KOYAMA TAKESHI;TANBA YUKO;AKIYAMA YUTAKA
分类号 G06F12/00;G06F13/36 主分类号 G06F12/00
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