发明名称 Ensuring minimum gate speed during startup of gate speed regulator
摘要 A computing device is disclosed comprising digital circuitry, and a gate speed regulator operable to generate a supply voltage applied to the digital circuitry. A frequency synthesizer generates a first reference frequency, and a propagation delay oscillator generates a first oscillation frequency in response to the supply voltage, wherein the first oscillation frequency is compared to the first reference frequency to generate a first error signal. A reference oscillator generates a second reference frequency in response to a reference voltage, and a startup oscillator generates a second oscillation frequency in response to the supply voltage, wherein the second oscillation frequency is compared to the second reference frequency to generate a second error signal. An adjustable circuit, responsive to the first and second error signals, adjusts the supply voltage applied to the digital circuitry.
申请公布号 US8390367(B1) 申请公布日期 2013.03.05
申请号 US201113027504 申请日期 2011.02.15
申请人 BENNETT GEORGE J.;WESTERN DIGITAL TECHNOLOGIES, INC. 发明人 BENNETT GEORGE J.
分类号 H03L7/06;G05F3/02 主分类号 H03L7/06
代理机构 代理人
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