ARCHITECTURE FOR DOWNLINK RECEIVER BIT RATE PROCESSOR,申请号EP20070838803-传众专利搜索

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发明名称	ARCHITECTURE FOR DOWNLINK RECEIVER BIT RATE PROCESSOR
摘要
申请公布号	EP2070204(B1)	申请公布日期	2013.02.27
申请号	EP20070838803	申请日期	2007.09.25
申请人	MEDIATEK INC.	发明人	VISHWANATHAN, KRISHNAN;MATHEW, DEEPAK;AARDOOM, ERIC;MARTINOT, LIDWINE;YAN, AIGUO;FISHER-JEFFES, TIMOTHY;KRIVACEK, PAUL, D.
分类号	H04B1/707;H04L1/00	主分类号	H04B1/707
代理机构		代理人
主权项
地址

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