| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of efficiently reducing a leak current without increasing the chip area. <P>SOLUTION: The semiconductor integrated circuit device includes cells A-1, B-1 and C-1 of identical logic. The cell B-1 has a cell width W2 larger than that of the cell A-1, and has a gate length L1 of a MOS transistor identical to that of the cell A-1. The cell C-1 has a cell width W2 identical to that of the cell B-1 and has a MOS transistor the gate length L2 of which is larger than that of the cell B-1. Compared to the cells A-1 and B-1, in the cell C-1, the circuit delay gets larger, but the leak current gets smaller. Therefore, for example, by replacing the cell A-1 adjacent to a vacant area with the cell B-1 and by replacing the cell B-1 in a path which has an excess timing with the cell C-1, the leak current is reduced without increasing the chip area. <P>COPYRIGHT: (C)2013,JPO&INPIT |
