发明名称 Data line bias circuit
摘要 A circuit for generating a voltage for pre-charging a data line. The circuit receives as input an ON/OFF signal which is typically the data bus line equalization control signal. The circuit also receives a varying power voltage. The circuit includes a bleeder which biases the data line at a voltage differing from said varying power voltage by a constant amount when the circuit is ON. The circuit consumes substantially zero power when OFF.
申请公布号 US5986474(A) 申请公布日期 1999.11.16
申请号 US19960585994 申请日期 1996.01.12
申请人 MOSEL VITELIC, INC. 发明人 CHUNG, JINYONG;LI, LI-CHUN;YOUNG, POCHUNG
分类号 G11C7/10;H04L25/02;(IPC1-7):H03K19/017 主分类号 G11C7/10
代理机构 代理人
主权项
地址