发明名称 |
SYNCHRONOUS FLASH MEMORY WITH VIRTUAL SEGMENT ARCHITECTURE |
摘要 |
An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device employs a virtual paging scheme that allows for the architecture of the memory to implement an efficient Flash memory structure internally. Externally, the memory logically maps the internal Flash architecture to an SDRAM compatible interface and virtual architecture, allowing for memory access and operation with a compatible SDRAM controller device. A double data rate interface is provided to allow data to be input and output from the memory in synchronization with both rising and falling edges of a clock signal. |
申请公布号 |
EP1423857(B1) |
申请公布日期 |
2013.01.23 |
申请号 |
EP20020794875 |
申请日期 |
2002.08.13 |
申请人 |
ROUND ROCK RESEARCH, LLC |
发明人 |
ROOHPARVAR, FRANKIE, FARIBORZ;WIDMER, KEVIN, C. |
分类号 |
G11C16/02;G11C16/08;G06F12/00;G06F12/02;G11C8/06 |
主分类号 |
G11C16/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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