发明名称 DUAL-SIDE INTERCONNECTED CMOS FOR STACKED INTEGRATED CIRCUITS
摘要 A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.
申请公布号 KR20130007652(A) 申请公布日期 2013.01.18
申请号 KR20127029532 申请日期 2011.04.06
申请人 QUALCOMM INCORPORATED 发明人 CHANDRASEKARAN ARVIND;HENDERSON BRIAN
分类号 H01L25/065;H01L25/18 主分类号 H01L25/065
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