发明名称 |
MEMORY ARBITER WITH LATENCY GUARANTEES FOR MULTIPLE PORTS |
摘要 |
Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of differences for the port covering each of a plurality of access requests. Further, the method includes determining a delta of a priority value for the port based on the running sum of differences. Moreover, the method includes prioritizing the access by the plurality of ports according to associated priority values.
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申请公布号 |
US2013007386(A1) |
申请公布日期 |
2013.01.03 |
申请号 |
US201113171484 |
申请日期 |
2011.06.29 |
申请人 |
SYNOPSYS INC.;WOLF PIETER VAN DER;GEUZEBROEK MARC JEROEN;BOONSTRA JOHANNES |
发明人 |
WOLF PIETER VAN DER;GEUZEBROEK MARC JEROEN;BOONSTRA JOHANNES |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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主权项 |
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地址 |
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