| 摘要 |
In order to latch and store a word line reset level voltage (negative voltage) which is set during reset operation, a word line driver includes PMOS transistors and NMOS transistors. The word line driver further includes a stress-reducing PMOS transistor and an NMOS transistor, and also a word line bias control circuit which controls and activates a supply bias during setting of a word line, start of resetting, and a reset period.
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