发明名称 Harmonic Rejection Mixer Architecture with Reduced Sensitivity to Gain and Phase Mismatches
摘要 A harmonic rejection mixer includes a first scaling circuit for scaling an RF signal to generate a plurality of scaled RF signals, a first switching stage for sampling the scaled RF signals using a first plurality of switching signals, and a second mixing stage for mixing the sampled RF signals with a second plurality of switching signals to generate a plurality of frequency translated signals having different phases. A combiner adds the frequency translated signals together to generate a first plurality of baseband versions of the RF signal. A first amplifier stage processes the first plurality of baseband versions to generate a second plurality of baseband versions. The mixer further includes a second scaling circuit for scaling the second plurality of baseband versions and a second amplifier stage to generate an in-phase baseband signal and a quadrature baseband signal from the scaled second plurality of baseband versions.
申请公布号 US2012322398(A1) 申请公布日期 2012.12.20
申请号 US201113331792 申请日期 2011.12.20
申请人 MAXLINEAR, INC. 发明人 PULLELA RAJA;PAIDI VAMSI;BHATIA RAHUL
分类号 H04B1/10 主分类号 H04B1/10
代理机构 代理人
主权项
地址