| 摘要 |
A word line driving signal control circuit of a semiconductor memory apparatus provided with a sub-redundancy cell array includes a fuse unit configured to generate a redundancy enable signal in response to a bank active signal and an address signal, and a repair determination unit configured to activate one of a normal word line driving signal, a redundancy word line driving signal, and a sub-redundancy word line driving signal in response to the bank active signal and the redundancy enable signal.
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