发明名称 |
ENCODING/DECODING CIRCUIT |
摘要 |
An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.
|
申请公布号 |
US2012314858(A1) |
申请公布日期 |
2012.12.13 |
申请号 |
US201213593133 |
申请日期 |
2012.08.23 |
申请人 |
MIYAUCHI SHIGENORI;YAMAGUCHI ATSUO;RENESAS ELECTRONICS CORPORATION |
发明人 |
MIYAUCHI SHIGENORI;YAMAGUCHI ATSUO |
分类号 |
H04L9/00 |
主分类号 |
H04L9/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|