发明名称 AMPLIFICATION CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide an amplification circuit that has a high voltage input stage capable of withstanding a common mode input voltage that is an arbitrary multiple voltage of a rated supply voltage without requiring an additional process. <P>SOLUTION: The input stage of the amplification circuit comprises: first differential pair transistors 10 connected with input terminals IN<SB POS="POST">1</SB>, IN<SB POS="POST">2</SB>; first input stage current biasing means 20 connected to N1VDD; a first input stage cascode transistor group 30 connected to the first differential pair transistors 10 and the first input stage current biasing means 20; a second input stage cascode transistor group 40 connected to the first differential pair transistors 10; and an input stage bias adjustment circuit 60 for adjusting a bias voltage such that absolute values of V<SB POS="POST">GS</SB>and V<SB POS="POST">GD</SB>of the first differential pair transistors 10, first input stage cascode transistor group 30 and second input stage cascode transistor group 40 are within VDD when a common mode input voltage varying from 0 V to N1VDD is input. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012238929(A) 申请公布日期 2012.12.06
申请号 JP20110104766 申请日期 2011.05.09
申请人 WASEDA UNIV 发明人 INOUE YASUAKI
分类号 H03F3/45 主分类号 H03F3/45
代理机构 代理人
主权项
地址