发明名称 PHASE-LOCKED LOOP CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a phase-locked loop circuit that prevents a stationary phase error due to a leak at an input section of a voltage-controlled oscillation circuit. <P>SOLUTION: The phase-locked loop circuit having a phase comparison circuit for detecting a phase difference between a reference clock signal and a feedback clock signal, a charge pump circuit for outputting a current depending on the detected phase difference to a first capacitance, and the voltage-controlled oscillation circuit for generating an output clock signal of an oscillation frequency depending on a control voltage based on a charge stored in the first capacitance holds a first voltage at a first time after the completion of output of the current from the charge pump circuit to the first capacitance, generates a current depending on a leakage current flowing into the input section of the voltage-controlled oscillation circuit on the basis of the first voltage thus held, and outputs a compensation current depending on the generated current to the first capacitance via a current mirror circuit to thereby suppress variations in the control voltage due to the leakage current. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012231447(A) 申请公布日期 2012.11.22
申请号 JP20120012292 申请日期 2012.01.24
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 ASANO KOSHO
分类号 H03L7/093;H03K5/26;H03L7/08 主分类号 H03L7/093
代理机构 代理人
主权项
地址