发明名称 WAFER LEVEL IC ASSEMBLY METHOD
摘要 A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced.
申请公布号 US2012288998(A1) 申请公布日期 2012.11.15
申请号 US201213554580 申请日期 2012.07.20
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 LEE CHIEN HSIUN;CHAO CLINTON;LII MIRNG JI;KARTA TJANDRA WINATA
分类号 H01L21/78 主分类号 H01L21/78
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