| 摘要 |
This document provides apparatus and methods for providing low latency response from a processor to the interrupts collected from peripheral devices. In an example, an apparatus can collect interrupt requests from a plurality of peripheral devices, and can communicate interrupt information to a processor. Certain examples can reduce the quantity of processor general purpose inputs and outputs configured to receive the peripheral device interrupts in comparison to systems where the peripheral device interrupts are directly coupled to the processor.
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