DIGITAL PLL CIRCUIT AND CLOCK GENERATION METHOD

摘要

PROBLEM TO BE SOLVED: To provide a digital PLL circuit in which a pull-in operation is not affected by restriction of a range of a phase difference detection value.

SOLUTION: A digital PLL circuit has: a digital phase detector 10 detecting a phase difference between a master clock and a slave clock, and outputting a phase difference detection value within a range of a length of 2π; a correction part 11 for correcting the phase difference detection value to a phase value not limited to the range depending on a comparison result between the phase difference detection value and a threshold; and a slave clock generation part 15 for generating the slave clock depending on the phase value outputted from the corrector.

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