发明名称 Skip based control logic for first in first out buffer
摘要 Skip based control logic for first in first out buffer is disclosed. In one embodiment, an isochronous data packet placed in an isochronous receive first in first out (IRFIFO) buffer coupled to an isochronous receive direct memory access (IRDMA) is detected. Further, a header of the isochronous data packet is read. Furthermore, a validity of the isochronous data packet is determined. Also, a read operation of remaining data of the isochronous data packet is skipped if the isochronous data packet is determined as invalid.
申请公布号 US8291133(B2) 申请公布日期 2012.10.16
申请号 US201113229774 申请日期 2011.09.12
申请人 RAIKAR RAYESH KASHINATH;KOMMINENI VIJAYA BHASKAR;AKULA SANTOSH KUMAR;KOTIKALAPUDI RANJITH KUMAR;GANGADHAR VINAY;LSI CORPORATION 发明人 RAIKAR RAYESH KASHINATH;KOMMINENI VIJAYA BHASKAR;AKULA SANTOSH KUMAR;KOTIKALAPUDI RANJITH KUMAR;GANGADHAR VINAY
分类号 G06F3/00;G06F13/00 主分类号 G06F3/00
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