发明名称 Phase locked loop
摘要 A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.
申请公布号 US8289057(B2) 申请公布日期 2012.10.16
申请号 US201213351745 申请日期 2012.01.17
申请人 KAWAMOTO TAKASHI;RENESAS ELECTRONICS CORPORATION 发明人 KAWAMOTO TAKASHI
分类号 H03L7/06 主分类号 H03L7/06
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