| 摘要 |
PURPOSE: An internal clock signal generating circuit and an operating method thereof are provided to minimize an operation property of a delay locked loop by preventing the malfunction of the delay locked loop due to a PVT skew. CONSTITUTION: A variable delay line(320) includes an initial variable delay unit and outputs a DLL clock signal by delaying an input clock signal with time corresponding to a delay control signal. A delay replication modeling unit(340) outputs a feedback clock signal by delaying a DLL clock signal with clock delay element modeling time. A phase comparison unit(350) generates a delay control signal by comparing the input clock signal with the feedback clock signal. [Reference numerals] (310) Input buffering unit; (320) Variable delay line; (321) Initial variable delay unit; (330) Output buffering unit; (340) Delay replication modeling unit; (350) Phase comparison unit; (360) Power voltage detection unit
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