| 摘要 |
A sample-and-hold (S/H) circuit is provided. The S/H circuit generally comprises a sampling switch, a sampling capacitor, and a correction network. The sampling switch that receives an analog input signal is actuated and deactuated by a timing signal. The sampling capacitor is coupled to the sampling switch at a sampling node so as to receive the analog input signal when the sampling switch is actuated and to store a voltage of the analog input signal when the sampling switch is deactuated. The correction network has at least one row of varactor cells such that each varactor cell is coupled to the sampling node and wherein each varactor cell in the row receives a reference voltage. Additionally, each varactor cell receives at least one of a plurality of control signals. |
