Integrated circuit test method and test apparatus

摘要

A method (200) for locating a fault in an integrated circuit (100) having a plurality of digital outputs coupled to compaction logic (140) in a test mode of the integrated circuit, the compaction logic comprising at least one output for providing a test response is disclosed. The method comprises the steps of: providing a simulation model of the integrated circuit (210); providing the simulation model with a plurality of test patterns (220); receiving a plurality of simulated test responses to said test patterns (230); defining a plurality of bits in the plurality of responses, said bits defining a signature of the fault (240); providing the integrated circuit with a further plurality of test patterns (250); receiving a plurality of test responses to said further plurality of test patterns (260); and checking the plurality of responses for the presence of the signature (270). This method provides improved fault detectability for an IC subjected thereto.