| 摘要 |
Provided are a method and device for testing a signal timing sequence, relating to the technical field of testing. In the present invention, if a rising-edge sampling is carried out on a signal to be tested, then when the signal to be tested is at a rising edge, a control module controls to output a high level, and an enable module outputs a predetermined signal; when a clock signal is at a rising edge, the control module controls to output a low level, and the enable module stops outputting the predetermined signal; if a falling-edge sampling is carried out on the signal to be tested, then when the signal to be tested is at a rising edge, the control module controls to output a high level, and the enable module outputs a predetermined signal; and when the clock signal is at a falling edge, the control module controls to output a low level, and the enable module stops outputting. The number of rising edges of the predetermined signal successively outputted by the enable module is counted, and the establishment time and retention time of the timing sequence of the signal to be tested are determined according to the counted number of rising edges of the predetermined signal. The automatic testing of the signal timing sequence is realized with high accuracy, improving the working efficiency of testing the signal timing sequence, and reducing the development cost of hardware.
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