发明名称 Frequency Offset Tracking and Jitter Reduction Method Using Dual Frequency-locked Loop and Phase-locked Loop
摘要 A method is provided for tracking large static or low-frequency frequency offset, such as SSC, in clock recovery of data communication or phase-locked loops based on a dual frequency-locked loop and phase-locked loop architecture. Instant PFD outputs are filtered to separate the phase errors due static/low-frequency frequency offset from the other phase mis-alignment. The static/low-frequency instant errors are used to drive a frequency-locked loop to track out static/low-frequency frequency offset completely. The phase-locked loop only needs to track the instant phase alignment other than the static/low-frequency frequency offset. Its gain or loop bandwidth does not need to be high so that the intrinsic jitter due to high gain or loop bandwidth can be avoided.
申请公布号 US2012200324(A1) 申请公布日期 2012.08.09
申请号 US201113021675 申请日期 2011.02.04
申请人 WANG HUI 发明人 WANG HUI
分类号 H03L7/08 主分类号 H03L7/08
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