发明名称 LOCKING SIGNAL GENERATION CIRCUIT AND DELAY LOCK LOOP INCLUDING THE SAME
摘要 PURPOSE: A locking signal generating circuit and a locked delay loop including the same are provided to perform a delay locked operation by using a comparison value or the change of the comparison value after the phase of a clock signal is compared with the phase of an external clock. CONSTITUTION: A delay unit(110) generates an output clock by delaying an input clock. A replica delay unit(120) generates a feedback clock by delaying the output clock. A phase comparing unit(130) generates a first signal, a second signal, and a third signal. A locking signal generating unit(140) generates a locking signal in response to the first to third signals. A delay value control unit(150) controls a delay value of the delay unit in response to the comparison result of the phase comparing unit and maintains a delay value of the delay unit when the locking signal is activated.
申请公布号 KR20120087642(A) 申请公布日期 2012.08.07
申请号 KR20110008971 申请日期 2011.01.28
申请人 SK HYNIX INC. 发明人 NA, KWANG JIN
分类号 G11C11/407;H03L7/081 主分类号 G11C11/407
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