Architecturally independent noise sensitivity analysis of integrated circuits having a memory storage device and a noise sensitivity analyzer

摘要

Method of analyzing noise sensitivity of integrated circuits having at least one memory storage device and a noise sensitivity analyzer. In one embodiment, the noise sensitivity analyzer includes a circuit reservoir, a circuit parser and a circuit evaluator. The circuit reservoir is configured to receive and store a model of a circuit having at least one memory storage device to be analyzed. The circuit parser is configured to identify nodes of the model. The circuit evaluator is configured to apply a large test current to each of the nodes for multiple circuit states of the at least one memory storage device and determine which of the nodes are sensitive nodes.