发明名称
摘要 <p>A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.</p>
申请公布号 JP4987904(B2) 申请公布日期 2012.08.01
申请号 JP20090098040 申请日期 2009.04.14
申请人 发明人
分类号 G11C16/02;G11C11/56;G11C16/06 主分类号 G11C16/02
代理机构 代理人
主权项
地址