发明名称 Data processing apparatus, memory controller, and access control method of memory controller
摘要 A data processing apparatus includes a memory which receives and outputs data with a predetermined data width, an operation circuit which outputs a read command or a write command to access the memory, and an access control circuit which replaces a part of first read data read from the memory with a partial data, and outputs partially replaced data as write data to the memory when receiving the write command and the partial data with a data width smaller than the predetermined data width associated with the write command, from the operation circuit. The access control circuit replaces a part of second read data which has been acquired in response to the read command outputted before, instead of the first read data, with the partial data, and outputs replaced partially data as the write data if the write command has been outputted in connection with a read command outputted before the write command.
申请公布号 US8234463(B2) 申请公布日期 2012.07.31
申请号 US20090453874 申请日期 2009.05.26
申请人 IKEUCHI TORU;AKAIKE YUKIHIKO;RENESAS ELECTRONICS CORPORATION 发明人 IKEUCHI TORU;AKAIKE YUKIHIKO
分类号 G06F12/00;G06F11/00;G06F11/16 主分类号 G06F12/00
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