| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a method for determining select-to-output delay of a multiplexer. <P>SOLUTION: A circuit has a first multiplexer 21 and a second multiplexer 22. The structure of the first multiplexer is substantially identical to the structure of the second multiplexer. The first multiplexer has a first data input lead 23, a second data input lead 24, a select input lead 25 and an output lead 26. The second multiplexer has a select input lead 29 and an output lead 30. The output lead of the second multiplexer is coupled to the select input lead of first multiplexer. An oscillating signal exists on the output lead of the second multiplexer. The output lead of the first multiplexer is coupled to the select input lead of the second multiplexer. A first logic level always exists on the first data input lead of the first multiplexer. A second logic level always exists on the second data input lead of the first multiplexer. <P>COPYRIGHT: (C)2012,JPO&INPIT |
