| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve a problem where a data read error becomes more likely to occur if the capacity of a capacitative element is reduced in a conventional DRAM. <P>SOLUTION: A plurality of cells are connected to one main bit line MBL_m. Each of the cells has a sub bit line SBL_n_m and 2 to 32 memory cells (MC_n_m_1, and so on). Each of the cells also comprises a selection transistor STr_n_m and a readout transistor RTr_n_m. The gate of the readout transistor RTr_n_m is connected to the sub bit line SBL_n_m. Because the parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential information on the capacitative element of each memory cell can be amplified by the readout transistor RTr_n_m without errors and can be output to the main bit line MBL_m. <P>COPYRIGHT: (C)2012,JPO&INPIT |
