发明名称 |
IMPLEMENTING SEMICONDUCTOR SOC WITH METAL VIA GATE NODE HIGH PERFORMANCE STACKED TRANSISTORS |
摘要 |
A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node.
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申请公布号 |
US2012175626(A1) |
申请公布日期 |
2012.07.12 |
申请号 |
US201113005089 |
申请日期 |
2011.01.12 |
申请人 |
ERICKSON KARL R.;PAONE PHIL C.;PAULSEN DAVID P.;SHEETS, II JOHN E.;UHLMANN GREGORY J.;WILLIAMS KELLY L.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ERICKSON KARL R.;PAONE PHIL C.;PAULSEN DAVID P.;SHEETS, II JOHN E.;UHLMANN GREGORY J.;WILLIAMS KELLY L. |
分类号 |
H01L27/092;H01L21/8238 |
主分类号 |
H01L27/092 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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