发明名称 Transmission system where a first device generates information for controlling transmission and latch timing for a second device
摘要 To provide a semiconductor device including a data input circuit and a data output circuit connected to a plurality of data input/output terminals, where at least one of the data input circuit and the data output circuit fetches data in response to multi-phase clock signals having different phases to be timing signals for fetching data, and adjusts a valid range for fetching data to be substantially uniform for each of the multi-phase clock signals. According to the present invention, the window width of data can be made uniform by individually adjusting the multi-phase clock signals that are input or output timing signals, and thus characteristics of the semiconductor device can be improved.
申请公布号 US8209560(B2) 申请公布日期 2012.06.26
申请号 US20090547863 申请日期 2009.08.26
申请人 ISHIKAWA TORU;ELPIDA MEMORY, INC. 发明人 ISHIKAWA TORU
分类号 G06F1/12;G06F13/42;H04L7/00 主分类号 G06F1/12
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