Wafer system processing method, involves extending electrical plated through-hole from one semiconductor layer into another semiconductor layer through insulation layer, where latter semiconductor layer is partially removed to expose hole

摘要

The method involves arranging an insulation layer (107) i.e. silicon-on-insulator wafer, between two semiconductor layers (103, 105) i.e. silicon wafers. An electrical-plated through-hole (109) is extended from one of the semiconductor layers into another semiconductor layer through the insulation layer. The latter semiconductor layer is partially removed by a sanding process and/or a plasma etching of the latter semiconductor layer for exposing the hole. Multiple recesses are formed in the latter semiconductor layer, and partially filled with electrical conductive material. An independent claim is also included for a wafer system comprising an insulation layer arranged between two semiconductor layers.