发明名称 PARTIALLY DEPELETED (DP) SEMICONDUCTOR-ON-INSULATOR (SOI) FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH A GATE-TO-BODY TUNNEL CURRENT REGION FOR THRESHOLD VOLTAGE (Vt) LOWERING AND METHOD OF FORMING THE STRUCTURE
摘要 Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.
申请公布号 US2012146146(A1) 申请公布日期 2012.06.14
申请号 US20100967329 申请日期 2010.12.14
申请人 ANDERSON BRENT A.;BRYANT ANDRES;LIANG JIALE;NOWAK EDWARD J.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ANDERSON BRENT A.;BRYANT ANDRES;LIANG JIALE;NOWAK EDWARD J.
分类号 H01L29/78;H01L21/336 主分类号 H01L29/78
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