| 摘要 |
<P>PROBLEM TO BE SOLVED: To fundamentally improve the accuracy of a replica circuit. <P>SOLUTION: A semiconductor device 10 includes a DLL circuit 70 for outputting an internal clock signal RLCLK obtained by delaying an external clock signal CK,/CK on the basis of at least a feedback clock signal RCLK1, a plurality of output buffers 64a for synchronizing with the internal clock signal RLCLK to output data, an output replica 73 being a replica of the output buffer 64a to generate a feedback clock signal RCLK1 in synchronization with the internal clock signal RLCLK and supply the feedback clock signal RCLK1 to the DLL circuit 70, and a clock tree 72 for receiving the internal clock signal RLCLK from the DLL circuit 70 to transmit the internal clock signal RLCLK to the plurality of output buffers 64a and the output replica 73. The clock tree 72 is configured so as to mutually and substantially equalize signal line loads of a plurality of transmission paths of the internal clock signal RLCLK which respectively go from the DLL circuit 70 to the plurality of buffers 64a and the output replica 73. <P>COPYRIGHT: (C)2012,JPO&INPIT |
