摘要 |
<p>An upright chain memory comprising: a two-level select transistor comprising first select transistors, which are upright transistors disposed in a matrix arrangement, and second select transistors, which are upright transistor formed respectively on the first select transistors; and a plurality of memory cells vertically connected in series on the two-level select transistor. This prevents both of the adjoining select transistors from being selected by their respectively shared gates, makes it possible to independently select a plurality of two-level select transistors respectively, and prevents a reduction in the memory capacity of a non-volatile memory device.</p> |
申请人 |
HITACHI, LTD.;SASAGO, YOSHITAKA;KINOSHITA, MASAHARU;MORIKAWA, TAKAHIRO;SHIMA, AKIO;KOBAYASHI, TAKASHI |
发明人 |
SASAGO, YOSHITAKA;KINOSHITA, MASAHARU;MORIKAWA, TAKAHIRO;SHIMA, AKIO;KOBAYASHI, TAKASHI |