发明名称 NON-VOLATILE MEMORY DEVICE AND PRODUCTION METHOD THEREOF
摘要 <p>An upright chain memory comprising: a two-level select transistor comprising first select transistors, which are upright transistors disposed in a matrix arrangement, and second select transistors, which are upright transistor formed respectively on the first select transistors; and a plurality of memory cells vertically connected in series on the two-level select transistor. This prevents both of the adjoining select transistors from being selected by their respectively shared gates, makes it possible to independently select a plurality of two-level select transistors respectively, and prevents a reduction in the memory capacity of a non-volatile memory device.</p>
申请公布号 WO2012070096(A1) 申请公布日期 2012.05.31
申请号 WO2010JP70769 申请日期 2010.11.22
申请人 HITACHI, LTD.;SASAGO, YOSHITAKA;KINOSHITA, MASAHARU;MORIKAWA, TAKAHIRO;SHIMA, AKIO;KOBAYASHI, TAKASHI 发明人 SASAGO, YOSHITAKA;KINOSHITA, MASAHARU;MORIKAWA, TAKAHIRO;SHIMA, AKIO;KOBAYASHI, TAKASHI
分类号 H01L27/105;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;H01L45/00 主分类号 H01L27/105
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