发明名称 |
ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN |
摘要 |
A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead. |
申请公布号 |
US2012133390(A1) |
申请公布日期 |
2012.05.31 |
申请号 |
US201113175168 |
申请日期 |
2011.07.01 |
申请人 |
DI JIA;SMITH SCOTT CHRISTOPHER |
发明人 |
DI JIA;SMITH SCOTT CHRISTOPHER |
分类号 |
H03K19/23 |
主分类号 |
H03K19/23 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|