| 摘要 |
<p>A device comprising an array of transistors, including: patterned conductive layers located at lower 18 and upper levels 20 in a stack of layers on a substrate 14, which patterned conductive layers define gate conductors 12 and source-drain electrodes 2,4,6 of the array of transistors; wherein the stack of layers further comprises a dielectric layer 16 below said lower level 18, and a further patterned conductive layer 8 below said dielectric layer 16; and wherein said further patterned conductive layer 8 both provides an electrical function in said array of transistors via said dielectric layer 16 , and defines openings via which the dielectric layer 16 serves to increase the strength of adhesion between the device substrate 14 and the patterned conductive layer 2,4,6 at said lower level. The further patterned conductive layer 8 may define an array of conductive elements for capacitive coupling via said dielectric layer 16 with overlying conductive elements 6 at said lower level 18. The further patterned conductive layer 8 may also define further gate conductors for the array of transistors. The stack may further include layers of organic material 18 to provide semiconductor channels between the source-drain electrodes, and gate dielectric elements 20 between the semiconductor channels 18 and overlying gate conductors 12.</p> |
