发明名称 |
Bump-on-lead flip chip interconnection |
摘要 |
A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.
|
申请公布号 |
US8188598(B2) |
申请公布日期 |
2012.05.29 |
申请号 |
US201113088647 |
申请日期 |
2011.04.18 |
申请人 |
PENDSE RAJENDRA D.;STATS CHIPPAC, LTD. |
发明人 |
PENDSE RAJENDRA D. |
分类号 |
H01L23/48;G01R31/26;H01L;H01L21/44;H01L21/56;H01L21/60;H01L21/66;H01L23/28;H01L23/498;H01L23/52;H01L29/40 |
主分类号 |
H01L23/48 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|