| 摘要 |
PURPOSE: An inner clock generating circuit and a flash memory including the same are provided to improve a data read speed by controlling the number of pulses and an operational frequency of an inner clock generating circuit. CONSTITUTION: An oscillator(310) is synchronized with an enable signal and outputs an oscillation signal. A delay unit delays the oscillation signal outputted from the oscillator. A clock pulse control unit(330) controls the number of pulses of the inner clock generated by synchronization with the oscillation signal outputted from the oscillator. A combination unit(340) generates the inner clock by logically operating a signal outputted from the clock pulse control unit and the signal outputted from the delay unit. |
