发明名称 |
SOURCE TIP OPTIMIZATION FOR HIGH VOLTAGE TRANSISTOR DEVICES |
摘要 |
The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.
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申请公布号 |
US2012119265(A1) |
申请公布日期 |
2012.05.17 |
申请号 |
US20100944959 |
申请日期 |
2010.11.12 |
申请人 |
SU RU-YI;YANG FU-CHIH;TSAI CHUN LIN;CHENG CHIH-CHANG;LIU RUEY-HSIN;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
SU RU-YI;YANG FU-CHIH;TSAI CHUN LIN;CHENG CHIH-CHANG;LIU RUEY-HSIN |
分类号 |
H01L29/78;H01L21/22;H01L21/336 |
主分类号 |
H01L29/78 |
代理机构 |
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地址 |
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