| 摘要 |
PURPOSE: A method for calibrating a robust gain and phase for a time-interleaved analog-to-digital converter is provided to eliminate problems at the convergence of adaptive correction by allowing an algorithm for signal specifications to be robust. CONSTITUTION: A TIADC(10) has the bit width of 12 bits. Two analog-digital converter cores(20,21) is operated on an analog input signal(12) to supply a digital output signal(14) which is expressed as y(n). The ADC cores sampled an input signal in defined alternating current sample time instants. Sample time instants are respectively controlled by an odd number rising edge(40ø1) and an even number rising edge(41ø2) of a clock signal(45). A multiplexer interleaves the outputs from two ADC cores.
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