发明名称 Method for fabricating an interlayer conducting structure of an embedded circuitry
摘要 A method for fabricating an interlayer conducting structure of an embedded circuitry is disclosed. In accordance with the method for fabricating an interlayer conducting structure of an embedded circuitry of the present invention, there is no laser conformal mask formed prior to laminating the first and second lamination plates. Instead, after the first and second lamination plates are laminated, a laser boring process is directly conducted to form a via hole. In such a way, even when there is an offset between the first and the second lamination plates in alignment, the risk of short circuit between different layers of lamination plates can be lowered without improving an interlayer offset value.
申请公布号 US8161639(B2) 申请公布日期 2012.04.24
申请号 US20100895824 申请日期 2010.09.30
申请人 CHANG CHIEN-WEI;LIN TING-HAO;LU YU-TE;KINSUS INTERCONNECT TECHNOLOGY CORP. 发明人 CHANG CHIEN-WEI;LIN TING-HAO;LU YU-TE
分类号 H01K3/10 主分类号 H01K3/10
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