| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a load driving device that optimizes timing between signals at load input terminals. <P>SOLUTION: A delay detection part 10 detects phase delay variation of a variation detection signal ref1 that has not passed through a CCD driver (driver IC) 4 and a variation detection signal ref2 that has passed through the CCD driver 4 both are output from a TG3 (driving signal generation means) that generates and outputs driving signals for driving a CCD1 and variation detection signals for detecting variation different from the driving signals; and a delay detection part 20 detects phase delay variation of a variation detection signal ref3 that has not passed through a CCD driver 5 and a variation detection signal ref4 that has passed through the CCD driver 5 that are output from the TG3. Feedback circuits 8 and 9 feed back these phase delay variations to the TG3, and the TG3 controls rising phase and falling phase of respective driving signals to be output based on the respective fed back phase delay variations. <P>COPYRIGHT: (C)2012,JPO&INPIT |
