发明名称 |
BUS SYSTEM AND DEADLOCK AVOIDANCE CIRCUIT THEREOF |
摘要 |
<P>PROBLEM TO BE SOLVED: To prevent the occurrence of deadlock in a system permitting simultaneous access to a plurality of slaves by split transactions. <P>SOLUTION: A preceding transaction information management unit 410 manages preceding transaction information issued prior to any of a plurality of slaves from a corresponding master. An issue stop determination unit 420 determines whether a transaction newly issued from the corresponding master becomes a factor of deadlock based on the preceding transaction information. A response output control unit 430 controls responses to return to the corresponding master based on the preceding transaction information. When responses to a preceding transaction from the plurality of slaves returned in order different from the order expected beforehand, a save buffer 470 saves the responses. <P>COPYRIGHT: (C)2012,JPO&INPIT |
申请公布号 |
JP2012073851(A) |
申请公布日期 |
2012.04.12 |
申请号 |
JP20100218612 |
申请日期 |
2010.09.29 |
申请人 |
SONY CORP |
发明人 |
AOKI SUMIE;KATANO YOSHITO |
分类号 |
G06F13/36;G06F12/00;G06F12/06;G06F15/173 |
主分类号 |
G06F13/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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