发明名称 |
Semiconductor memory device which stores plural data in a cell |
摘要 |
A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
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申请公布号 |
US8154930(B2) |
申请公布日期 |
2012.04.10 |
申请号 |
US20100775571 |
申请日期 |
2010.05.07 |
申请人 |
SHIBATA NOBORU;TANAKA TOMOHARU;KABUSHIKI KAISHA TOSHIBA |
发明人 |
SHIBATA NOBORU;TANAKA TOMOHARU |
分类号 |
G11C16/02;G11C16/04;G11C11/34;G11C11/56;G11C16/06;G11C16/12;G11C16/34 |
主分类号 |
G11C16/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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