发明名称 ERROR CORRECTION DECODER, MEMORY CONTROLLER, AND RECEIVER
摘要 <P>PROBLEM TO BE SOLVED: To increase the capability of correcting errors in LDPC code. <P>SOLUTION: An error correction decoder according to an embodiment repeatedly decodes data which has been encoded using nonregular LDPC code. The error correction decoder includes a parity inspection unit 104 which generates a temporary estimation word based on a check node-to-variable node external value, inspects the temporary estimation word for parity, and, if all check nodes satisfy parity inspection, determines the temporary estimation word to be a codeword. The error correction decoder includes a likelihood control unit 106 which, when a prescribed condition is satisfied which includes a possibility that no codeword is obtained even after repeat decoding is performed a prescribed number of times, executes weighting to increase the absolute magnitude of a check node-to-variable node external value which does not satisfy parity inspection by using a plurality of external value weights having a greater threshold or equal value according to the descending order of column weights of variable nodes where the maximum and minimum values are unequal. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012060450(A) 申请公布日期 2012.03.22
申请号 JP20100202095 申请日期 2010.09.09
申请人 TOSHIBA CORP 发明人 OBATA HARUKA;UCHIKAWA HIRONORI
分类号 H03M13/19 主分类号 H03M13/19
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