| 摘要 |
<p>A memory control device is provided with: a CPU (1); a flash ROM (4) for recording therein first information which has been subjected to an error correction encoding process and second information which has not been subjected to the error correction encoding process; an address line switch (5) which switches between a first path for interconnecting an address bus (2) and the ROM (4) so as to enable the CPU (1) to read the first information recorded in the ROM (4) and a second path for interconnecting the address bus (2) and the ROM (4) so as to enable erasure, write and read of the second information recorded in the ROM (4); a decoder (7) which subjects the first information recorded in the ROM (4) to error correction and decoding; and a data line switch (6) which switches between a third path for interconnecting the decoder (7) and a data bus (3) so as to transmit the information decoded by the decoder (7) to the data bus (3) and a fourth path for interconnecting the ROM (4) and the data bus (3) so as to enable erasure, write and read of the second information recorded in the ROM (4).</p> |
