| 摘要 |
<p>A jitter measuring circuit that is capable of measuring the amount of clock jitter and the amount of logic circuit delay jitter separately is provided. The jitter measuring circuit comprises a variable logic delaying section, a data holding section and a controller. The data holding section outputs predetermined data whenever a delay time of the variable logic delaying section is within a time period equivalent to one clock cycle. While the controller changes a delay time of the variable logic delaying section, it observes whether the data holding section outputs expected data and finds a marginal delay time which represents the amount of jitter. If the jitter measuring circuit operates on a power supply without power supply noise, the measured jitter has component of the clock signal only, and if it operates on a power supply with power supply noise, the jitter contains components of the clock signal plus the logic delay time variation.</p> |
