| 摘要 |
PURPOSE:To obtain a highly stable clock extracting circuit by comparing a frequency division output with a reference clock, applying the comparison output to a varactor diode connected in parallel to a tank circuit, and correcting a resonance frequency. CONSTITUTION:A phase comparator 6 detects the detuning of the tank circuit 1 as the phase shift of the output signal of a 1/8 frequency divider 4 and its output signal is passed through a low-pass filter 7 to extract the phase error of the frequency-divided signal of a clock of 64 kHz as to the frequency-divided signal of a clock of 6.312 MHz. This signal is applied to the cathode terminal of the varactor diode 2 added to the tank circuit 1 to control the tuning of the tank circuit 1. The output of the tank circuit 1 is inputted to a voltage comparator 3 to discriminate a reference voltage Vref and the ouptut is sent to the 1/8 frequency divider 4. Consequently, PLL operation is performed to reduce the detuning of the tank circuit 1 due to temperature variation, etc. |
